1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor memory device and to a corresponding semiconductor memory device.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor memory devices, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology. In particular, DRAM technology which is scaled down to below 100 nm generation provides big challenges.
Stack DRAM memory cell arrays of today have angled active area lines in respect to the bitlines in order to take into account that the node contacts (contacts of the selection transistors to the cell capacitors) have to pass by the bitlines to contact the capacitor above the bitline and that the bitline contacts must be centered under the respective bitlines.
Angled active area lines have disadvantages in respect to the array edges, as it is difficult to find space-saving printable solutions to terminate the lines. Angled active area lines create more overlay sensitivity for the array devices where usually the wordlines run perpendicular to the bitlines. Angled active area lines also reduce the contact area for the node contacts and the bitline contacts.